This invention is in the field of solid-state memory of the ferroelectric type. Embodiments of this invention are directed to circuit techniques for improving write and write-back signal margin in ferroelectric random access memories (FRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now portable or handheld devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, implantable medical devices, and the like.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by forming the capacitors above the transistor level, between overlying levels of metal conductors.
The data storage mechanism of FRAM cells is the charge-voltage hysteresis of the ferroelectric capacitor dielectric. The charge stored across the conductive plates of the ferroelectric capacitor depends on the voltage applied to the plates and also on the recent history of that voltage. If the voltage applied across the capacitor plates exceeds a “coercive” voltage, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage remains above coercive voltage, the capacitor exhibits a stored charge of Q1. Conversely, if an applied voltage is more negative than coercive voltage, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor its two polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. In the context of a ferroelectric capacitor, the change in polarization state that occurs upon application of a polarizing voltage is reflected by the amount of charge stored by the capacitor as a result.
Reading an FRAM memory cell can be destructive (i.e. a memory cell loses its data). As result of an FRAM memory cell losing its data after a read, the memory cell in an FRAM memory must be written back to the memory cell. This procedure is often called “write-back.” An FRAM memory cell may also be written to directly. This procedure is called a “write” to the FRAM memory cell. When a FRAM memory cell is written or written back, it is important that electrical noise surrounding the FRAM be kept as low as possible. In a case where electrical noise is high, the write or write-back of an FRAM cell may be corrupted by the electrical noise.